1. Field of the Invention
This invention relates to signal balancing in integrated circuits. More particularly it relates to signal balancing in system on chip integrated circuits. More specifically, it applies to balancing signal arrival time in IC designs between multiple random logic macros (RLM).
2. Background of the Invention
Currently, in order to balance signal arrival times between multiple RLMs, designers manually add buffers and make wiring adjustments by hand to adjust the signal's latency both within each RLM and at the top level of a design. Such a method is undesirable for the following reasons:
1) Adding the proper amount of delay buffers and adjusting wire delays greatly increases Turn Around Time (TAT);
2) When designing signal paths within each RLM, consideration must be taken to match other RLM's latencies;
3) RLM reuse between individual designs is complicated;
4) Any modification to a RLM or the top level of a design effects the entire signal path, possibly requiring the signal to be rebalanced, wasting previous manual efforts; and
5) Re-balancing a hierarchical clock tree involves discarding previous manual efforts and restarting adjustments.
Large variations in RLM size/load count result in large signal latency variations within RLMs.
One possible solution to this problem is to actually implement programmable delay logic into the integrated circuit itself. Once the integrated circuit is manufactured, the delays are calculated and actual delay logic can then be fixed. Of course, this approach has the attendant problems relating to having to design-in additional logic that would otherwise be unnecessary.